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Figure 64. Standby Management
Remark:
• Skip cycle is not allowed during the PFC startup phase to avoid that it interferes with the soft-start. That is why, skip cycle is enabled only when "pfcOK" is high.
• Each working phase of the burst mode starts smoothly as Pin 3 is grounded at the beginning of it. This soft-start capability is effective to avoid the audible noise that could possibly result from such a burst operation.
• The circuit leaves the standby mode when the output voltage goes below 95.5% of its regulation level and VPin1 is above 330 mV (300 mV + 30 mV hysteresis).
Oscillator / Synchronization Section
The oscillator generates the clock signal to set the PWM latch and turn the MOSFET on. The oscillator frequency is set by the capacitor that is applied to Pin 8. Typically, 820 pF force about 60 kHz. The maximum allowable oscillator frequency is 250 kHz. The clock frequency can also be driven by an external synchronization signal. This block contains two main parts (refer to Figure 66):
• The arrangement that consists of charging/discharging current sources, a switch and a comparator. When used in oscillator mode, a capacitor is connected between Pin 8 and ground. A current source (100 ^A) charges the Pin 8 capacitor until its voltage exceeds VoscH. At that moment, the comparator ("COMP_OSC") turns high and activates the discharge current source (200 ^A). As a consequence, Pin 8 actually sinks 100 ^A that discharge the oscillator capacitor to VoscL. At that moment, the comparator turns low and initiates a new charge phase. If the circuit is to be externally triggered, the synchronization signal must cross VoscL and VoscH to properly turn on and off the "COMP_OSC" comparator. Also the synchronization signal must be low impedance enough not to be distorted by the Pin 8 source and sink currents.
• The "storing circuitry" that contains a latch and some gates. The raising edge of the "COMP_OSC" output sets the "CLOCK Generation" latch to turn high the "CLK" signal. If the timing capacitor of Pin 7 is properly discharged (Vpin4 <50 mV leading to "CjOK" high), the PWM block is ready for a new cycle and "CLK" can force the signal "VSET" in high state. As a consequence, the PWM latch sets. In addition, "VSET" resets the "CLOCK Generation" latch to make it ready for the next oscillator cycle. The two inverters of Figure 66, simply generate some delay to ensure that "VSET" keeps high long enough to set the PWM latch and reset the "CLOCK Generation" latch (longer delay than that produced by the two gates, may actually be necessary). The oscillator / Synchronization block is designed to set the switching frequency.
However, the coil current can possibly be non zero at the end of a clock period and the circuit would enter Continuous Conduction Mode (CCM) if the MOSFET turned on in that moment. In order to prevent CCM, the "storing circuitry" of the oscillator / synchronization block, memorizes the "COMP_OSC" rising edge (thanks to the "CLOCK Generation" latch) and delays the next MOSFET conduction time until the coil current has totally vanished (that is until the signal "DT" is high - "DT" is generated by the current sense block so that it is high during the dead-time and low otherwise). In other words, CRM operation is obtained (refer to Figure 65).
Figure 66. Oscillator / Synchronization Block
Figure 65. Oscillator Timing Diagram
Figure 66. Oscillator / Synchronization Block
Figure 65. Oscillator Timing Diagram
- (When high, "UVLO" indicates that the circuit is not properly fed and it sets the Fault latch to turn off the circuit) Figure 67. The Current Source brings Vcc above 15 V and then Turns Off
Startup Sequence / VCC Management
At the moment when the PFC stage is plugged to the mains outlet, the internal current source starts charging the Vcc capacitor. More generally, the startup current source is enabled whenever Vcc drops below VccSTUP (7 V, typically). When Vcc exceeds the VccON level (typically 15 V for the NCP1605, 10.5 V for the NCP1605A), the current source turns off and the circuit starts pulsing.
The energy stored by the Vcc capacitor serves to feed the controller and some auxiliary supply must take over before Vcc drops below VccOFF (9 V, typically), that is, the level below which the circuit stops pulsing.
Hence, the circuit starts operating when the Vcc voltage exceeds VccON and stops pulsing when Vcc drops below VCCOFF. The hysteresis (6 V for the NCP1605, 1.5 V for the NCP1605A) prevents erratic operation as the Vcc crosses the VccON threshold.
Figure 67 shows the internal arrangement of this structure (the Vcc turn on threshold of Figure 67 is that of the NCP1605). One can note that the startup current source is on during the Vcc charging phase and off for the rest of the time. Hence, it spends no power during the PFC stage operation and in particular, in light load conditions. That is why the NCP1605(A) helps meet the most stringent standby requirements.
Remarks:
• Some circuitry (not represented in Figure 67) limits the HV pin current below 1 mA if the Vcc voltage is nearly below 1 V. This protects the circuit when the Vcc pin is accidentally grounded. The full current capability (around 15 mA) is obtained when Vcc exceeds about 1 V.
• The circuit is also kept off when the startup current source is on to make a clear distinction between the Vcc charge phase and the operating sequence (refer to "HVCS_ON" signal on block diagram).
Brown-Out Detection
The brown-out pin receives a portion of the input voltage (Vin)- As Vin is a rectified sinusoid, a capacitor must integrate the ac line ripple so that a voltage proportional to the average value of (Vin) is applied to the brown-out pin.
The brown-out block detects too low input voltage conditions. A hysteresis comparator monitors the Pin 2 voltage. Before operation, the PFC stage is off and the input bridge acts as a peak detector. Hence, the voltage applied to Pin 2 is:
Vpin2 = yiVac-
Rbo2
Rbol + Rbo2' After the PFC stage has started operation, the input voltage becomes a rectified sinusoid and the voltage applied to Pin 2 is:
Ac line
BO NOK
Ac line
BO NOK
Figure 68. Brown-Out Block i.e., about 64% of the previous value. Therefore, the same line magnitude leads to a VPin2 voltage that is 36% lower when the PFC is working than when it is off (refer to Figure 69). That is why the NCP1605(A) features a 50% hysteresis (VBOL = 50% VBOH).
When the circuit starts operation, the input voltage equates the ac line peak.
Hence, the initial threshold of the Brown-Out comparator, must be the upper one (VBO = VBOH = 1 V when the NCP1605 leaves the off mode).
When a brown-out condition is detected, the signal "BO_NOK" turns off the circuit (refer to block diagram).
Figure 69. Typical Input Voltage of a PFC Stage
Figure 68. Brown-Out Block
Figure 69. Typical Input Voltage of a PFC Stage
Thermal Shutdown (TSD)
An internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 150 °C typically. The output stage is then enabled once the temperature drops below about 100 °C (50 °C hysteresis).
The temperature shutdown keeps active as long as the circuit is not reset, that is, as long as Vcc keeps higher than VccRESET. The reset action forces the TSD threshold to be the upper one (150°C). This ensures that any cold startup will be done with the right TSD level.
Output Drive Section
The output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. The gate drive is kept in a sinking mode whenever the Undervoltage Lockout is active or more generally whenever the circuit is off (i.e., when the "Fault Latch" of the block diagram is high or when the HV current source is on). Its high current capability (-500 mA/+800 mA) allows it to effectively drive high gate charge power MOSFET.
Reference Section
The circuit features an accurate internal reference voltage (Vref). Vref is optimized to be ±3% accurate over the temperature range (the typical value is 2.5 V). Vref is the voltage reference used for the regulation and the overvoltage protection. The circuit also incorporates a precise current reference (Iref) that allows the Overcurrent Limitation to feature a ±6% accuracy over the temperature range.
OFF Mode
As previously mentioned, the circuit turns off in the following cases:
• When the high voltage, startup current source charges the Vcc capacitor.
• When one of the following major faults is detected:
• Incorrect feeding of the circuit ("UVLO" high when Vcc<VccOFF, VccOFF equating 9 V typically).
• Excessive die temperature detected by the thermal shutdown.
• Brown-Out condition.
• Undervoltage Protection.
• VPin13 higher than 2.5 V ("STDWN" of the block diagram turns high).
Generally speaking, the circuit turns off when the conditions are not proper for good operation. In this mode, the controller stops operating. The major part of the circuit sleeps and its consumption is minimized (< 500 ^A).
• All the blocks are off except:
1. The uVLo circuitry that keeps monitoring the VCC voltage and controlling the startup current source accordingly.
2. The TSD (thermal shutdown)
3. The "STDWN" latch that stores its output state.
4. The Undervoltage Protection ("UVP").
5. The brown-out circuitry. one must note that the comparator is reset during the latched-off phase so that its threshold is the upper one (1 V) when the circuit enters the active phase (refer to next "VCC sequences" section).
6. The high voltage, startup current source when the circuit is in startup phase (that is when VCC is lower than VCCSTUP).
|
VCC Conditions |
"OFF" is Low (no condition forces the circuit off) |
"OFF" is High (due to some protection like the thermal shutdown) |
|
Vcc exceeds VccON ^ the circuit enters the working phase |
The startup current source is disabled The circuit is fully active |
The startup current source is disabled The circuit is in OFF state |
|
Vcc drops below VccOFF ^ the circuit enters the latched-off phase |
The circuit is in OFF state The brown-out block resets during the latched-off phase so that its comparator threshold is forced to be the upper one (1 V) |
The circuit is in OFF state The brown-out block resets during the latched-off phase so that its comparator threshold is forced to be the upper one (1 V) |
|
Vcc goes below VccSTUP ^ the circuit enters the startup phase |
The high voltage, startup current source turns on to charge VCC. The drive output and the "pfcOK" are in low state (the circuit is off) All the circuit blocks are reset except: The thermal shutdown (TSD) and the brown-out block that keep operating The "STDWN" latch. |
The high voltage, startup current source turns on to charge VCC. The drive output and the "pfcOK" are in low state (the circuit is off) All the circuit blocks are reset except: The thermal shutdown (TSD) and the brown-out block that keep operating The "STDWN" latch. |
|
Vcc goes below VccRESET ^ the circuit resets |
The high voltage, startup current source is on. The whole circuitry is reset including the "TSD" and the "STDWN" latch. After reset, the TSD threshold is 150°C and the output of the "STDWN latch" is low. |
The high voltage, startup current source is on. The whole circuitry is reset including the "TSD" and the "STDWN" latch. After reset, the TSD threshold is 150°C and the output of the "STDWN latch" is low. |
The figures on the following pages portray the circuit behavior during a startup phase:
• In case of normal conditions (Figure 70).
• As a function of the brown-out pin voltage (Figure 71).
• The Pin 3 capacitor is discharged and kept grounded along the OFF time, to initialize it for the next operating sequence, where it must be slowly and gradually charged to offer some soft-start.
• The output of the "Vton processing block" is grounded
Vcc Sequences
The following table summarizes the state of the circuit in accordance to the VCC level.
Remarks:
The Vcontrol signal does not necessarily reach its clamp level (3.7 V) depending of the load and of the system time constants. In particular, if the circuit starts operation in light load and if the bulk capacitor is not too large, the output voltage Vout generally exceeds the regulation level while Vcontrol keeps below its upper limit.
The output voltage exhibits a 100 or 120 Hz ripple (at twice the line frequency). This ripple is also present in the Vcontrol voltage even if it is attenuated due to the regulation low bandwidth. Like that of Vout, this ripple is not represented in Figure 70, for the sake of the clarity.
vccon
Vcc vccon
VccOFF
VccSTUP
vout
Vqut Regulation Level vcontrol
Flag1
Circuit State
pfcOK
Vcontrol MAX = 3.7 V
These re-activations of "Flag1" result from Vout 100 or 120 Hz ripple (not represented here for the sake of clarity)
JZIMM^
Drive Output
Figure 70. Startup Phase in Normal Conditions
VOUT
Brown-Out Pin Voltage
Drive Output
Circuit State pfcOK
- VCCON
The Circuit is Off > Low Consumption
The Circuit is Off > Low Consumption
VCCOFF
VCCSTUP
Vout Regulation Level
Figure 71. Startup and Brown Out Conditions
When the high voltage, startup current source is on, the brown-out is active and its threshold is the upper one (Vbo = VboH = 1 V).
Fault Management Block
When any of the following faults is detected: brown-out ("BO_NOK"), Undervoltage ("UVP"), shutdown ("STDWN"), Die Overtemperature ("TSD"), the circuit immediately turns off and recovers operation as soon as the fault disappears.
In case of UVLO (Vcc too low to allow operation), the circuit keeps off until the end of the next Vcc charge phase by the HV startup current source.
The following block diagram details the function.
|
Internal Thermal Shutdown | ||
|
TSD ' |
- UVP^ Stdwn f—A | |
BO NOK
uvloA
uvloA
(Vcc<VccOFF)
Figure 72. Fault Management Block
(Vcc<VccOFF)
Figure 72. Fault Management Block
- The above figure shows how the circuit recovers after a brown-out event.
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